Memory circuit architecture
US6208551A · kind A · utility
1Cited by
5References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 22, 1999 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Oct 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM made in monolithic form, the cells of which each include a MOS transistor and a capacitor, a second electrode of which is common to all cells of a same row and is covered with an insulator, the insulator being coated with independent conductive elements distributed on a same horizontal plane, two neighboring elements being biased to respective high and low levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.