Nonvolatile semiconductor memory device
US6208560A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2000 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Jun 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND cell unit comprising a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20 V is applied to the control gate of any selected one of the memory cells, 0 V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11 V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data "0" can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.