Semiconductor memory device having resistive bitline contact testing
US6208572A · kind A · utility
64Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2000 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Jun 12, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having resistive bitline contact testing includes memory cells, and wordline logic devices for concurrently activating two adjacent memory cells. The two adjacent memory cells are activated concurrently to allow higher current through a bitline contact for improved detection of resistive bitline contacts. A test cell may also be included to test the integrity of the bitline contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.