Computer system controller and method with processor write posting hold off on PCI master memory request
US6209067A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 1995 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Dec 4, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1694
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system including a memory controller provides a series of queues between a processor and a peripheral component interconnect (PCI) bus and a memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A write posting queue for processor to PCI writes must be flushed before a PCI device can access memory. If the queue is not empty when the PCI device requests a memory read, the PCI device is forced to retry the operation while the write posting queue is flushed. Also, while the queue is flushed, the processor is prevented from further posting to the queue. A timer provides a further temporary time that the processor is precluded from posting to allow enough time for the PCI master to retry the operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.