Source synchronous interface between master and slave using a deskew latch
US6209072A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 1997 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | May 6, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A source synchronous interface between a master device and slave device is described. A master device having a plurality of deskew latches is coupled to a slave device via a bus. The master device communicates commands and first timing information to the slave device via the bus. In response, the slave device communicates data and second timing information to the master device via the bus. When data is communicated from the slave device to the master device, the data is stored in one of the plurality of deskew latches until accessed by the master device. The plurality of deskew latches ensure that the master device will always read valid data for the full range of skew of the first and second timing information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.