Method and apparatus for two-stage address generation
US6209076A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 24, 1998 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Jul 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is an apparatus and method for two-stage address generation that uses pipelining to avoid one level of latency in certain address-generation situations. The first level of the present invention contains redundant three-lever hardware that performs pre-add logic on 32-bit or 16-bit operands. The pre-add logic circuit for 32-bit operands comprises three carry-save adders. For 16-bit operands, the pre-add logic circuit comprises a four-port three-level 16-bit adder. The second stage comprises a three-logic level adder that adds two operands. The method of the present invention avoids one level of latency for simple address generation, although both stages are always utilized. For complex address generation, both latency cycles are required. Regarding dependent generation, the present invention provides a single-cycle latency bypass datapath that also avoids one level of latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.