Dual damascene process for carbon-based low-K materials
US6211061A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1999 |
| Grant date | Apr 3, 2001 |
| Priority date | — |
| Expiry date | Oct 29, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76808
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a dual damascene structure in a carbon-based, low-K material. The process begins by providing a semiconductor structure having a first metal pattern thereover, wherein the first metal pattern has a first barrier layer thereon. An organic dielectric layer is formed on the first barrier layer, and a hard mask layer is formed on the dielectric layer. The hard mask layer and the dielectric layer are patterned to form a trench. A second barrier layer is formed over the hard mask layer and on the bottom and sidewalls of the trench. A barc layer is formed over the second barrier layer, thereby filling the trench. The barc layer, the second barrier layer, and the dielectric layer are patterned to form a via opening, preferably using a photoresist mask. The barc layer is patterned without faceting the edges of the via opening due to the second barrier layer. The barc layer and the etch mask are removed by the dielectric layer etch. The first barrier layer and the second barrier layer are removed. A third barrier layer is formed on the bottom and sidewalls of the trench, on the sidewalls of the via opening, and on the first metal pattern through the via opening. The tren…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.