Memory cell layout for reduced interaction between storage nodes and transistors
US6211544A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Mar 18, 1999 |
| Grant date | Apr 3, 2001 |
| Priority date | — |
| Expiry date | Mar 18, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/908
Abstract
A memory cell, in accordance with the invention, includes a trench formed in a substrate, and an active area formed in the substrate below a gate and extending to the trench. The active area includes diffusion regions for forming a transistor for accessing a storage node in the trench, the transistor being activated by the gate. The gate defines a first axis wherein a portion of the active area extends transversely therefrom, the portion of the active area extending to the trench. The trench has a side closest to the portion of the active area, the side of the trench being angularly disposed relative to the gate such that a distance between the gate and the side of the trench is greater than a minimum feature size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.