Method and apparatus for testing chips

US6211571A · kind A · utility

Assignee

• Fraunhofer-Gesellschaft zur förderung der angewandten Forschung e.V. · DE

Inventors

• Elke Zakel · Falkensee, DE
• Frank Ansorge · Berlin, DE
• Paul Kasulke · Berlin, DE
• Andreas Ostmann · Berlin, DE
• Rolf Aschenbrenner · Berlin, DE
• Lothar Dietrich · Berlin, DE

Key dates

• Filing date: Sep 6, 1996
• Grant date: Apr 3, 2001
• Expiry date: Sep 6, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/15173
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Method and apparatus for the testing of substrates which are provided with a wiring structure, in particular, chips (21), in conjunction with which, by means of a solder-deposit carrier (25) which is provided with a structured, electrically conductive coating (12) with bond pads (17) for the arranging of solder deposits (28) and their transfer to correspondingly arranged bond pads (22) of a substrate (21), an electrical check of the wiring structure of the substrate (21) takes place during the transfer of the solder deposits (28).