Test circuit and method for measuring switching point voltages and integral non-linearity (INL) of analog to digital converters
US6211803A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 12, 1998 |
| Grant date | Apr 3, 2001 |
| Priority date | — |
| Expiry date | Nov 12, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit and method is described whose objective is built-in self-test (BIST) for analog-to-digital converters (ADCS) and input logic gates of an integrated circuit. The technique converts the switching point voltage, or logic threshold, into a binary-encoded digital value which can be compared to upper and lower limits to decide pass or fail. Every clock cycle, the output of the ADC is compared to a digital output value, and if the output is larger than the reference a logic 0 is output, otherwise a logic 1. This series of ones and zeroes is fed back to an analog low pass filter connected to the ADC's input, and also to a digital averaging circuit which counts the number of ones in a constant interval. The number of ones is linearly proportional to the switching point voltage. Measuring the switching point voltages for a multi-bit ADC allows on-chip calculation of the differential non-linearity (DNL), the integral non-linearity (INL) and the maximum DNL and INL can be compared against upper limits to determine whether the ADC passes or fails the test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.