Semiconductor memory device
US6212110A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1999 |
| Grant date | Apr 3, 2001 |
| Priority date | — |
| Expiry date | Dec 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Switch MOSFETS are interposed between a sense amplifier disposed in a dynamic RAM and complementary bit lines. After signal voltages were read out by the selecting operations of the word lines from a plurality of dynamic memory cells selected, to the plurality of pairs of complementary bit lines in accordance with their individual storage informations, the switch control signal of the switch MOSFETs is changed from a select level to a predetermined intermediate level. The switch MOSFETs, supplied with the intermediate potential at their gates, are turned ON as a result that sense nodes are set to one level in accordance with the amplifying operations of the sense amplifier. An amplification signal generated by the amplifying operation is transmitted through the column select circuit to input/output lines in response to the column select signal, and the switch control signal is returned from the intermediate potential level to the select level in response to the selecting operation of the column select circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.