Process for forming vertical semiconductor device having increased source contact area

US6214673A · kind A · utility

Assignee

• Intersil Corporation · US

Inventors

• Thomas E. Grebs · Smethport, US
• Jason R. Trost · Drums, US

Key dates

• Filing date: Jul 9, 1999
• Grant date: Apr 10, 2001
• Expiry date: Jul 9, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/663

Abstract

A process for forming a vertical semiconductor device having increased source contact area comprises forming a gate and a well region in a silicon substrate. Using dopant of a second conductivity type, a shallow source region is formed in the well region, and a first oxide layer is deposited over the gate and the source and well regions. The first oxide layer of oxide is etched to form a first oxide on the substrate adjacent the gate, a thin nitride layer is deposited over the gate and source regions, and a second oxide layer is deposited over the nitride layer and etched to form a second oxide spacer separated from the first oxide spacer and substrate by the nitride layer. These spacers are used as a mask to selectively remove the thin nitride layer from the gate and substrate and portions of the gate polysilicon and source region and thereby form in the source region a recessed portion comprising vertical and horizontal surfaces. Using a dopant of a first conductivity type, a shallow emitter region is formed in the well region underlying the recessed portion of the source region. The second oxide spacer and thin nitride layer separating it from the first oxide spacer are removed …