Method of fabricating self-aligned ultra short channel
US6214677A · kind A · utility
15Cited by
6References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 22, 1999 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | Oct 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/665
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a self-aligned ultra short channel. The method uses double spacers as a hard mask, so that DRAM with the ultra short channel is formed in a self-aligned process. This method not only reduces the channel length, but also adjusts the dopants in lightly doped drains (LDD) at a side of the storage node opening and at the side of the bit line, respectively, so as to optimize the device property.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.