Method of fabricating self-aligned silicide
US6214709A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 4, 1998 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | Aug 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating salicide. A metal layer is formed on a substrate with a polysilicon gate and a source/drain region. A material layer is then formed on the metal layer, wherein the material is selected to produce compressive stress as compressive stress is produced on the substrate and to produce tensile stress as tensile stress is produced in the substrate. The material layer needs to be chosen with the same stress produced by the metal layer. A thermal process is then performed on the substrate to form a silicide on the polysilicon gate and the source/drain region. The material layer and the unreacted metal layer are removed and therefore the salicide process is accomplished.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.