Method for improving wafer topography to provide more accurate transfer of interconnect patterns
US6214722A · kind A · utility
4Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 5, 1999 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | Apr 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing an interconnect on a wafer having an edge region and an interior region comprises the steps of: forming an insulating layer on the wafer having an interior region and an edge region; forming an opening penetrating through the insulating layer in the interior region and removing a portion of the insulating layer to expose a surface of the wafer in the edge region, simultaneously; forming a conductive layer over the insulating layer and the exposed surface of the wafer and filling the opening; and patterning the conductive layer to form a wire in the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.