Method and apparatus for maximizing the random access bandwidth of a multi-bank DRAM in a computer graphics system
US6215497A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 12, 1998 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | Aug 12, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphics sub-system having a 2-D graphics accelerator, a 3-D graphics accelerator and an embedded DRAM memory. The embedded DRAM memory serves as a frame buffer memory and/or a temporary storage memory for the 2-D graphics accelerator. The embedded DRAM memory also serves as a cache memory for the 3-D graphics accelerator or an external central processing unit (CPU). The embedded DRAM memory is logically divided into a plurality of independent banks, thereby resulting in a relatively fast average memory cycle time. More specifically, the embedded DRAM memory processes one transaction per clock cycle for accesses with no bank conflicts. The memory access time for any transaction (e.g., a bank-conflict access) is no greater than the memory cycle time plus the memory access time minus 1 clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.