Prefetch queue responsive to read request sequences
US6216208A · kind A · utility
25Cited by
5References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1997 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | Dec 29, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A prefetching control system provided for a processor. The prefetching queue may include an arbiter, a cache queue and a prefetch queue. The arbiter issues requests including read requests. Responsive to a read request, the cache queue issues a control signal. The prefetch queue receives the control signal and an address associated with the read request. When the received address is a member of a pattern of read requests from sequential memory locations, the prefetch queue issues a prefetch request to the arbiter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.