Method and apparatus for expanding instructions
US6216221A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1997 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | Dec 31, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor includes a decoder, a queue, and a renamer. The decoder is adapted to receive a program instruction and decode the program instruction to provide a first decoded instruction. The first decoded instruction includes a plurality of instruction bits. The queue is coupled to the decoder and adapted to store the first decoded instruction. The renamer has a first input port and a first and second output port. The renamer is coupled to the queue and adapted to receive the first decoded instruction at the input port, provide the first decoded instruction on the first output port, change at least one of the instruction bits to generate a second decoded instruction, and provide the second decoded instruction on the second output port. A method for expanding program instructions in a microprocessor having a renamer is provided. The renamer includes a first input port and first and second output ports. The method includes receiving a first decoded instruction in the first input port. The first decoded instruction includes a plurality of instruction bits. At least one of the instruction bits of the first instruction is changed to generate a second instruction. The first decoded …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.