Method of fabricating semiconductor device having a dual-gate
US6218229A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1997 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Oct 31, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
Abstract
The method of fabricating a semiconductor device having a dual-gate provides a semiconductor substrate with a gate insulating film formed on a first portion and a second portion thereof and a polysilicon layer formed on the gate insulating film. A first dopant of a first conductive type is implanted in the polysilicon layer covering the first portion, and a second dopant of a second conductive type is implanted in the polysilicon layer covering the second portion. Then, the polysilicon layer covering the first portion is selectively etched using a first mask to form a first gate, and a third dopant of the first conductive type is implanted to form source/drain LDD regions on both sides of the first gate. Thereafter, the polysilicon layer covering the second portion is selectively etched using a second mask to form a second gate, and a fourth dopant of the second conductive type is implanted to form source/drain LDD regions on both sides of the second gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.