Method of forming a buried bitline in a vertical DRAM device
US6218236A · kind A · utility
19Cited by
14References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 28, 1999 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Jan 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/053
Abstract
A method of forming a shallow outdiffused buried bitline in a vertical semiconductor memory device is disclosed which utilizes annealing and oxidation to drive-in and pile-up the dopant atom into an outdiffused region. The anneal/oxidation which is carried out at two different temperature ranges allows for fabricating buried bitlines having the lowest resistance as possible at a maximum dopant concentration, yet being formed near the surface interface of the vertical pillars. Semiconductor memory devices containing the outdiffused buried bitline regions are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.