Method of fabricating bottom electrode
US6218261A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 15, 1999 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Apr 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/712
Abstract
A method of fabricating a bottom electrode is provided. A dielectric layer comprising a first opening is formed on the substrate. A conductive layer is formed on the dielectric layer to fill the first opening. A first patterned mask layer comprising a second opening is formed on the conductive layer. An isotropic etching step is performed on the conductive layer with the first patterned mask layer serving as a mask. A recess with a non-vertical sidewall is formed on the conductive layer under the second opening. The first patterned mask layer is removed. The conductive layer is patterned to form a bottom electrode with the recess. A hemispherical grained silicon layer is formed on the bottom electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.