Method of manufacturing interconnect
US6218294A · kind A · utility
2Cited by
6References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 16, 1999 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Apr 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76802
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing an interconnect. A first conductive layer is formed on the wafer. Portions of the first conductive layer are removed to form a wire in the interior region and to expose the surface of the wafer in the edge region, simultaneously. An insulating layer is formed on the wire and the wafer. An opening is formed to penetrate through the insulating layer and exposes the wire. A second conductive layer is formed on the insulating layer and fills the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.