Area efficient column select circuitry for 2-bit non-volatile memory cells
US6218695A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 1999 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Jun 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit that includes a series of parallel elongated diffusion bit lines and an array of 2-bit non-volatile memory cells connected between the diffusion bit lines. Column select circuits are located at the ends of the diffusion bits lines that selectively connect the diffusion bit lines to a bit line decoder circuit to read appropriate signals from selected memory cells. A series of metal jumpers extend over and connect the ends of the diffusion bit lines. By connecting both ends of the diffusion bit lines together, the metal jumpers allow the diffusion bit lines to be longer without increasing resistance, so that a single pair of column select circuit control a large number of memory cells to increase the area efficiency of the memory array. Conversely, the metal jumpers reduce the resistance in shorter diffusion bit lines, thereby increasing memory array endurance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.