Back-biased MOS device and method
US6218708A · kind A · utility
90Cited by
4References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 25, 1998 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Feb 25, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/378
Abstract
An MOS device has source and drain regions of a first conductivity formed in a well of a second conductivity, the well of the second conductivity being formed in an upper surface of a bulk material of the first conductivity. Source and drain potentials are applied to the source and drain regions, respectively, while a separate bias potential is routed to the well through a conductive sub-surface layer of the second conductivity which is located spaced from and beneath an upper surface of the bulk material and which is shorted to the well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.