Patent · US Expired

Programmable input/output circuit for FPGA for use in TTL, GTL, GTLP, LVPECL and LVDS circuits

US6218858A · kind A · utility

49Cited by

5References

5Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Suresh M. Menon · Sunnyvale, US
Yogendra Bobra · San Jose, US
Atul V. Ghia · San Jose, US
Arch Zaliznyak · San Jose, US

Key dates

Filing date	Jan 27, 1999
Grant date	Apr 17, 2001
Priority date	—
Expiry date	Jan 27, 2019

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/17788
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A programmable input/output structure comprised of three input circuits and one output circuit coupled to the pin of an FPGA with the input circuits and output circuits being selectively enabled by programming bits so that input signals may be accepted from TTL, GTL, GTLP, LVPECL or LVDS type external circuits. The programming bits can also selectively enable an output driver to simultaneously drive the same pin of the FPGA as an output with signals which are either TTL or GTL or GTLP compatible. Further, the slew rate of the output driver is programmable between slow, medium or fast.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.