D-type flip-flop circiut
US6218878A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 16, 1998 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Apr 16, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/289
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is provided a D-type flip-flop circuit which is improved in terms of operating frequency. First and second current supplying circuits are provided as sources for supplying currents to first and third differential circuits for inputting data and to second and fourth differential circuits for holding data in a master circuit and a slave circuit. Further, timing for supplying the currents to the respective differential circuits for inputting and holding data are controlled by first and second clock signals, respectively. The D-type flip-flop circuit is improved in terms of operating frequency by optimizing timing for writing input data and timing for holding data by arranging the first clock signal so as to have a certain delay with respect to the second clock signal. Further, the D-type flip-flop circuit is improved with respect to the operating frequency also by optimizing the value of the currents supplied to the respective differential circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.