Memory having user programmable AC timings
US6219288A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2000 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Mar 3, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A SRAM module provides programmability of AC timings such that an end user can adjust or "tweak" the AC timings to maximize system performance. A variable delay circuit is placed in the path between a signal (e.g., data signal or address signal)and the SRAM set-up and hold register which allows the user to shift the setup-and-hold window by selected increments. The delay circuit can either advance or retard the AC timings. A delay program controlling the delay circuit is selected in one of two ways; either by a default AC timing program stored in a ROM device and preset by the manufacturer, or by a private JTAG instruction and AC programming data input by the user through the JTAG state machine provided on the SRAM chip. Once the optimum delay (or advance) is selected to optimize the SRAM to the cache system this user program may be permanently burned into the default ROM such that the optimum timings are used thereafter as the default.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.