False exception for cancelled delayed requests
US6219758A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 1998 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Mar 25, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A central processor uses virtual addresses to access data via cache logic including a DAT and ART, and the cache logic accesses data in the hierarchical storage subsystem using absolute addresses to access data, a part of the first level of the cache memory includes a translator for virtual or real addresses to absolute addresses. When requests are sent for a data fetch and the requested data are not resident in the first level of cache the request for data is delayed and may be forwarded to a lower level of said hierarchical memory, and a delayed request may result in cancellation of any process during a delayed request that has the ability to send back an exception. A delayed request may be rescinded if the central processor has reached an interruptible stage in its pipeline logic at which point, a false exception is forced clearing all I the wait states while the central processor ignores the false exception. Forcing of an exception occurs during dynamic address translation (DAT) or during access register translation (ART). A request for data signal to the storage subsystem cancellation is settable by the first hierarchical level of cache logic. A false exception signal to the f…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.