Method of making semiconductor devices with graded top oxide and graded drift region
US6221737A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1999 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Sep 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a semiconductor device such as a diode or MOSFET provided in a thin semiconductor film on a thin buried oxide is disclosed, in which the lateral semiconductor device structure includes at least two semiconductor regions separated by a lateral drift region. A top oxide insulating layer is provided over the thin semiconductor film and a conductive field plate is provided on the top oxide insulating layer. In order to provide enhanced device performance, a portion of the top oxide layer increases in thickness in a substantially continuous manner, while a portion of the lateral drift region beneath the top oxide layer decreases in thickness in a substantially continuous manner, both over a distance which is at least about a factor of five greater than the maximum thickness of the thin semiconductor film. This structure is achieved by a method including the steps of forming an oxidation mask including silicon nitride on the thin semiconductor film, and then patterning a portion of the oxidation mask with a series of sequential openings of different widths, a portion of the openings having a width less than the maximum thickness of the top oxide insulation layer. The t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.