Signal monitoring circuit for detecting asynchronous clock loss
US6222392A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 1999 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Jan 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/10
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An apparatus detects the loss of an asynchronous input signal and generates a reset signal that is synchronous to a system clock signal. The apparatus detects the loss of the input signal and generates a first output signal. The first output signal is delayed by a predetermined number of clock cycles, and a second output signal is generated to indicate a sustained loss of the input signal. A signal monitoring circuit is provided to confirm the loss of the input signal and generate a third output signal. The reset signal is generated only if the signal loss is both sustained and confirmed. Accordingly, the apparatus will not be unnecessarily reset as a result of noise that delays or accelerates the arrival of an edge of the asynchronous input signal. The apparatus may also be configured to monitor the loss of multiple asynchronous input signals in a multi-port channel by cascading a plurality of sub-circuits, each of which is configured to receive at least one input signal and independently generate a local reset signal. Hence, the apparatus is capable of performing a graceful recovery if any of the input signals are lost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.