Universal package and method of forming the same
US6222737A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 23, 1999 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Apr 23, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49144
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A chip module comprising a chip array which includes an interconnect substrate having opposed, generally planar surfaces and a first interconnect pad array disposed on at least one of the surfaces thereof. Attached to the interconnect substrate is at least one integrated circuit chip of the chip array which is electrically connected to the first interconnect pad array. The chip module further comprises a package which itself comprises a main body defining a cavity sized and configured to receive the chip array and having a generally planar interconnect shelf which extends within the cavity and includes a second interconnect pad array disposed thereon. The package also includes a lid which is attachable to the main body. The chip array is insertable into the cavity such that the first and second interconnect pad arrays are in aligned contact with each other and the attachment of the lid to the main body encloses and seals the chip array within the package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.