SRAM cell arrangement and method for manufacturing same

US6222753A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Bernd Goebel · Dresden, DE
• Emmerich Bertagnolli · Munich, DE
• Josef Willer · Riemerling, DE
• Barbara Hasler · Munich, DE
• Paul-Werner von Basse · Wolfratshausen, DE

Key dates

• Filing date: Dec 20, 1999
• Grant date: Apr 24, 2001
• Expiry date: Dec 20, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B10/12

Abstract

An SRAM cell arrangement which includes six MOS transistors per memory cell wherein each transistor is formed as a vertical transistors. The MOS transistors are arranged at sidewalls of trenches. Parts of the memory cell such as, for example, gate electrodes or conductive structures fashioned as spacers are contacted via adjacent, horizontal, conductive structures arranged above a surface of a substrate. Connections between parts of memory cells occur via third conductive structures arranged at the sidewalls of the depressions and word lines via diffusion regions that are adjacent to the sidewalls of the depressions within the substrate, via first bit lines, via second bit lines and/or via conductive structures that are partially arranged at different heights with respect to an axis perpendicular to the surface. Contacts contact a plurality of parts of the MOS transistors simultaneously.