Configuration memory architecture for FPGA
US6222757A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 1998 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Feb 25, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A configuration memory architecture for an FPGA that eliminates the need for a regular array of word lines and bit lines is disclosed. The memory is comprised, in the preferred embodiment, of a plurality of memory bytes. Each memory byte has eight SRAM latches, a single flip flop and a one-of-eight decoder having a data input coupled to the inverting output of the flip flop and eight individual data outputs, each of which is coupled to a data input of one of the SRAM latches. The decoder also has address and write control inputs which are coupled to a state machine or other programmable device that controls the sequencing of the loading operation to load configuration data into the memory. The flip flops of all the memory bytes are coupled together in a serpentine shift register. Loading of configuration data involves shutting all paths through the decoder down, shifting all configuration bits for the "0" position SRAM latch of each memory byte into the shift register, and setting the address bits to the decoder so as to create a conductive path in each memory byte from the output of the flip flop to the data input of the selected SRAM latch. The process is then repeated for all ot…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.