Erasable memory device and an associated method for erasing a memory cell therein
US6222764A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1999 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Dec 13, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically erasable memory device includes a substrate and a plurality of single poly layer memory cells in the substrate. Each single poly layer memory cell includes a first MOS transistor in a first region in the substrate and spaced apart source and drain regions. Each single poly layer memory cell further includes a capacitor having a first electrode overlying a second region in the substrate and an insulating layer therebetween, and a third region in the second region defining a second electrode. An erasing circuit selectively erases the single poly layer memory cell by supplying a first voltage reference of a first polarity to the spaced apart source and drain regions, a second voltage reference of a second polarity to the first region, and a third voltage reference of the second polarity to the second electrode of the capacitor. The first and second voltage references bias the first MOS transistor so that the third voltage reference for erasing the single poly layer memory cell does not cause a junction breakdown of the first MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.