Slew tolerant clock input buffer and a self-timed memory core thereof
US6222791A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2000 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Jun 15, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a clock input buffer for a self-timed memory core that is configured to store data. The self-timed memory core generates a reset signal for resetting the clock input buffer. The clock input buffer includes a latch functioning block and a model latch functioning block. The latch functioning block receives a clock signal for generating a control signal for triggering the self-timed memory core to perform an I/O operation. On the other hand, the model latch functioning block receives the clock signal and the control signal for generating a delayed inverse clock signal. The model latch functioning block provides the delayed inverse clock signal to the latch functioning block for generating the control signal. The model latch functioning block is configured to have the same delay and a delay that varies at approximately the same rate as a delay in the latch functioning block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.