Method and apparatus for floating point (FP) status word handling in an out-of-order (000) Processor Pipeline
US6223278A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 5, 1998 |
| Grant date | Apr 24, 2001 |
| Priority date | — |
| Expiry date | Nov 5, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3854
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for performing floating point (FP) instruction handling is provided. A floating point store status word (FSTSW) instruction is inserted within a plurality of micro-ops corresponding to a plurality of FP instructions and the plurality of micro-ops are ordered for execution. In another aspect, a processor is provided for executing a plurality of floating point (FP) instructions. The processor includes a fetcher/decoder unit to retrieve a plurality of FP instructions from a memory structure and generate a plurality of micro-ops from the FP instructions. The processor further generates a floating point store status word (FSTSW) instruction and includes a scheduler unit to re-order the micro-ops for execution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.