Stitching design rules for forming interconnect layers
US6225013A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 1999 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | May 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/31764
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for stitching a plurality of mask regions including the steps of (1) defining cut regions on the mask regions, wherein the cut regions adjoin the edges of the mask regions to be stitched, (2) implementing a first set of design rules in the cut regions, and (3) implementing a second set of design rules outside of the cut regions. The mask regions can be formed on a single reticle or on a plurality of separate reticles. In one embodiment, the first set of design rules specifies that trace patterns in the cut regions have widths greater than trace patterns outside of the cut regions. In another embodiment, the first set of design rules specifies that trace patterns in the cut regions have a minimum spacing greater than trace patterns outside of the cut regions. In yet another embodiment, the first set of design rules specifies that trace patterns can be formed entirely within the cut regions. The stitching method can also include the steps of (1) defining a cut line on a wafer, (2) aligning first and second mask regions with the cut line such that transparent regions of the first and second mask regions have a controlled amount of overlap with respect to the cut line, and (3)…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.