Method of forming salicide in embedded dynamic random access memory

US6225155A · kind A · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Yung-Chang Lin · Kaohsiung, TW
• Tung-Po Chen · Taichung, TW
• Jacob Chen · Hsinchu, TW

Key dates

• Filing date: Dec 8, 1998
• Grant date: May 1, 2001
• Expiry date: Dec 8, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/05

Abstract

In a method of forming a salicide layer in an embedded dynamic random access memory, a thin oxide layer, a silicon nitride layer and a thick oxide layer are sequentially formed over a substrate after performing an annealing process to a source/drain region. The insulating layer on a gate and a source/drain region in a logic region and a gate in a memory region. Salicide layers are formed on the three regions mentioned above. Formation of the salicide layers can lower resistance of the three regions, increase speed and can avoid forming a salicide layer on the source/drain region in the memory region. Thus, current leakage can be avoided. In addition, the step of forming a salicide layer is conducted after the annealing process of the source/drain region, so problems of thermal stability and inter-diffusion of impurities in the polysilicon layer can also be solved.