Method of manufacturing bottom electrode of capacitor
US6225160A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 1999 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | Apr 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/712
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a bottom electrode of a capacitor. A first dielectric layer is formed on a substrate. A cap layer is formed on the first dielectric layer. A second dielectric layer is formed on the cap layer. A node contact hole is formed to penetrate through the second dielectric layer, the cap layer and the first dielectric layer. A liner layer is formed on a sidewall of the node contact hole. A restraining layer is formed on the second dielectric layer. A patterned conductive layer is formed on a portion of the restraining layer and fills the node contact hole. A selective hemispherical grained layer is formed on the patterned conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.