Method for STI-top rounding control
US6225187A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1999 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | Apr 1, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76232
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This present discloses a method for STI top rounding control, the steps comprising: (a) providing a semiconductor substrate; (b) forming an oxide layer on the substrate; (c) forming a hard mask on the oxide layer; (d) forming a photoresist pattern with an opening exposing the hard mask at a predetermined STI trench region on the hard mask; (e) etching the exposed hard mask and the underlying oxide layer within the opening in sequence, and continuously over-etching to remove part of the semiconductor substrate to form a window lower than the surface of the oxide layer; and (f) using the photoresist pattern and the hard mask as an etching mask, removing part of the exposed semiconductor substrate in the window to form an STI trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.