Method of fabricating crack resistant inter-layer dielectric for a salicide process
US6225209A · kind A · utility
4Cited by
11References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 1998 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | Sep 10, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a crack resistant inter-layer dielectric for a salicide process. The method includes forming an insulating layer on a provided substrate, forming a planarized inter-layer dielectric layer on the insulating layer, and performing a short-duration thermal treatment to increase the density of the inter-layer dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.