Method of manufacturing semiconductor device having multilayer wiring
US6225217A · kind A · utility
35Cited by
5References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1999 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | Nov 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76813
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first insulating film with a dielectric constant lower than that of a silicon oxide film is formed on a semiconductor substrate. Next, a metal film or a second insulating film, which has degrees of moisture absorption and deformation in an oxygen plasma process and exposure to a resist releasing solution equal to or less than those of a silicon oxide film, is formed on the first insulating film. Then, the metal film or the second insulating film is patterned to a prescribed pattern. An opening is formed in the first insulating film using the metal film or the second insulating film as a mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.