Passivation of porous semiconductors for improved optoelectronic device performance and light-emitting diode based on same
US6225647A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 1998 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | Jul 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/8264
Abstract
A method for substantially improving the photoluminescent performance of a porous semiconductor, involving the steps of providing a bulk semiconductor substrate wafer of a given conductivity, wherein the substrate wafer has a porous semiconductor layer of the same conductivity as the bulk semiconductor substrate wafer, and the porous semiconductor layer is made up of a plurality of pores interspersed within a plurality of nanocrystallites, wherein each of the pores is defined by a pore wall and each of the nanocrystallites has a given thickness. Next, in the method, at least one monolayer layer of passivating material is generated on the pore wall of each of the pores, to passivate the porous semiconductor layer. The one layer of passivating material substantially eliminates dangling bonds and surface states which are associated with the porous semiconductor layer. The resulting passivated porous semiconductor layer exhibits a quantum efficiency of approximately 5 percent. In one embodiment of the present invention, the one monolayer of passivating material is an oxide which is generated by placing the bulk semiconductor substrate wafer into a furnace set a predetermined temperatur…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.