Integrated circuit which minimizes parasitic action in a switching transistor pair
US6225673A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 1999 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | Feb 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (13) includes a P-epi substrate (51) having first and second n+ isolation layers (53, 54) buried therein, the first and second isolation layers being respectively coupled to ground and to a supply voltage (VCC). A contact region (52) of the substrate is closely adjacent a first isolation layer, is spaced from the second isolation layer, and is coupled to ground. First and second P-epi portions (57, 58) of the substrate are disposed within the first and second isolation layers. The first portion includes an n+ source region (62) disposed in a p-well (61) which is closely adjacent the first isolation layer in the vicinity of the contact region, and includes an n+ drain region (68). The second portion includes an n+ source region (77) coupled to the drain region in the first portion, and an n+ drain region (82) coupled to the supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.