Sameer Pendharkar
231Patents
14h-index
88Co-inventors
89Inventor score
Filing activity: Nov 20, 1998 → Aug 17, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6424005B1 | LDMOS power device with oversized dwell | Electricity | 94 | Expired |
| US6211552A | Resurf LDMOS device with deep drain region | Electricity | 69 | Expired |
| US7187033B2 | Drain-extended MOS transistors with diode clamp and methods for making the same | Electricity | 56 | Expired |
| US6395593B1 | Method of manufacturing high side and low side guard rings for lowest parasitic performance in an H-bridge configuration | Electricity | 54 | Expired |
| US6441431B1 | Lateral double diffused metal oxide semiconductor device | Electricity | 43 | Expired |
| US6160290A | Reduced surface field device having an extended field plate and method for forming the same | Electricity | 28 | Expired |
| US8759879B1 | RESURF III-nitride HEMTs | Electricity | 21 | Active |
| US6919603B2 | Efficient protection structure for reverse pin-to-pin electrostatic discharge | Electricity | 20 | Expired |
| US8890248B2 | Bi-directional ESD protection circuit | Electricity | 20 | Active |
| US8264038B2 | Buried floating layer structure for improved breakdown | Electricity | 18 | Active |
| US7427795B2 | Drain-extended MOS transistors and methods for making the same | Electricity | 18 | Expired |
| US7235451B2 | Drain extended MOS devices with self-aligned floating region and fabrication methods therefor | Electricity | 17 | Expired |
| US7238986B2 | Robust DEMOS transistors and method for making the same | Electricity | 16 | Expired |
| US6468837B1 | Reduced surface field device having an extended field plate and method for forming the same | Electricity | 14 | Expired |
| US9865729B1 | Laterally diffused metal oxide semiconductor with segmented gate oxide | Electricity | 13 | Active |
| US7135759B2 | Individualized low parasitic power distribution lines deposited over active integrated circuits | Electricity | 13 | Expired |
| US6225673A | Integrated circuit which minimizes parasitic action in a switching transistor pair | Electricity | 12 | Expired |
| US7745294B2 | Methods of manufacturing trench isolated drain extended MOS (demos) transistors and integrated circuits therefrom | Electricity | 12 | Active |
| US8253193B2 | MOS transistor with gate trench adjacent to drain extension field insulation | Electricity | 12 | Active |
| US7414287B2 | System and method for making a LDMOS device with electrostatic discharge protection | Electricity | 10 | Expired |
| US6624481B1 | ESD robust bipolar transistor with high variable trigger and sustaining voltages | Electricity | 10 | Expired |
| US7005354B2 | Depletion drain-extended MOS transistors and methods for making the same | Electricity | 10 | Expired |
| US7713825B2 | LDMOS transistor double diffused region formation process | Electricity | 10 | Active |
| US7045903B2 | Integrated power circuits with distributed bonding and current flow | Electricity | 10 | Expired |
| US9685545B2 | Isolated III-N semiconductor devices | Electricity | 9 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.