Stacked microelectronic assembly and method therefor
US6225688A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 1999 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | Feb 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked microelectronic assembly and its resulting structure includes a flexible substrate having a plurality of attachment sites, test contacts and conductive terminals, and including a wiring layer with leads extending to the attachment sites. The assembly includes a plurality of microelectronic elements assembled to the attachment sites and electrically interconnecting the microelectronic elements and the leads. The flexible substrate is folded so as to stack at least some of the microelectronic elements in substantially vertical alignment with one another to provide a stacked assembly with the conductive terminals exposed at the bottom end of the stack and the test contacts exposed at the top end of the stack. The assembly may be made using a dam and or a spacer to facilitate the folding process. Two stacked microelectronic assemblies may be stacked together by providing a first stacked assembly with a plurality of connection pads exposed at the top end and providing a second stacked assembly with a plurality of solder balls connected to the terminals at the bottom end. The first and second assemblies may be stacked by connecting the solder balls to the connection pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.