Integrated level two cache and controller with multiple ports, L1 bypass and concurrent accessing
US6226722A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 1994 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | May 19, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system wherein data retrieval is simultaneously initiated in both and L2 cache and main memory, which allows memory latency associated with arbitration, memory DRAM address translation, and the like to be minimized in the event that the data sought by the processor is not in the L2 cache (miss). The invention allows for any memory access to be interrupted in the storage control unit prior to any memory signals being activated. The L2 and memory access controls are in a single component, i.e. the storage control unit (SCU). Both the L2 and the memory have a unique port into the CPU which allows data to be directly transferred. This eliminates the overhead associated with storing the data in an intermediate device, such as a cache or memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.