Coded frame synchronizing method and circuit
US6226768A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1998 |
| Grant date | May 1, 2001 |
| Priority date | — |
| Expiry date | Apr 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/004
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A coded frame synchronization method for decoding coded information sent every frame includes the steps of: (a) receiving a coded frame having error detection or correction codes, each of which is provided every predetermined number of bits, error detection or correction codes being added to the coded frame in accordance with a predetermined pattern; (b) pulling the coded frame in synchronization by performing an error detection process every predetermined number of bits to be compared with results of the error detection process and thus detecting a phase of the error detection or correction codes; and (c) recognizing a leading end of the coded frame on the basis of the phase of the error detection or correction codes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.