Non-selective epitaxial depostion technology
US6228733A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1999 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Sep 23, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D10/051
Abstract
Base layer formation without the use of selective epitaxial deposition is described. The process begins with the deposition of a seed layer of polysilicon over both the field oxide and the wafer surface that lies between them. An opening in said seed layer is then formed, between the areas of field oxide (and overlying an N+ buried layer). Non-selective epitaxial growth is then used to deposit the transistor's base layer. This automatically results in the formation of self aligned butted contacts of polysilicon on either side of the base. Manufacture of the transistor is completed in the usual way--emitter formation, emitter poly contact formation, ILD deposition, etc.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.