Process for forming metal interconnects with reduced or eliminated metal recess in vias
US6228757A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1998 |
| Grant date | May 8, 2001 |
| Priority date | — |
| Expiry date | Mar 5, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for manufacturing a semiconductor device having metal interconnects reduces or eliminates the recessing of metal in the vias, particularly when the metal in the vias is aluminum or an aluminum alloy. The process includes forming a via in a device layer of the semiconductor device. A barrier layer is formed over the device layer and a metal layer is formed over the barrier layer. The metal layer also fills the via to form a via structure. A portion of the metal layer is then removed and a remaining portion of the metal layer forms a conductive structure having a sidewall extending from a surface of the barrier layer. A spacer is formed along the sidewall of the conductive structure and a portion of the barrier layer is removed using the spacer to protect the via structure adjacent the surface of the device layer. In particular, the spacer protects a portion of the via structure that does not overlap with the conductive structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.